Download A Pipelined Multi-core MIPS Machine: Hardware Implementation by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul PDF

By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

This monograph is predicated at the 3rd author's lectures on laptop structure, given in the summertime semester 2013 at Saarland college, Germany. It includes a gate point building of a multi-core desktop with pipelined MIPS processor cores and a sequentially constant shared memory.

The ebook includes the 1st correctness proofs for either the gate point implementation of a multi-core processor and in addition of a cache established sequentially constant shared reminiscence. This opens easy methods to the formal verification of synthesizable for multi-core processors within the future.

Constructions are in a gate point version and therefore deterministic. against this the reference versions opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness facts of the shared reminiscence on the gate point are the most technical contributions of this work.

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5 Drivers and Main Memory 55 yin yin α OC y y α β β Fig. 27. Open collector driver and its timing diagram collector drivers, and main memory. 5 that a design that works in the digital model also works in the detailed hardware model. For tristate drivers and main memory this will not be the case. 1 Open Collector Drivers and Active Low Signal A single open collector driver y and its detailed timing is shown in Fig. 27. If the input yin is 0, then the open collector driver also outputs 0. If the input is 1, then the driver is disabled.

6 (3) The term switching function comes from electrical engineering and stands for a Boolean function. 6 Boolean Algebra 27 We define the support S(f ) of f as the set of arguments a, where f takes the value f (a) = 1: S(f ) = {a | a ∈ Bn ∧ f (a)} . If the support is empty, then e = 0 computes f . Otherwise we set m(a) . 19) ↔ ∃a ∈ S(f ) : a = x (3) ↔ x ∈ S(f ) ↔ f (x) = 1 . Thus, equations e = 1 and f (x) = 1 have the same solutions. 16 we conclude e ≡ f (x) . 20 is called the complete disjunctive normal form of f .

In order to arrive at the abstraction of the digital hardware model later, we count clock edges – clock edge i marks the start of cycle i in the detailed model. The circuit clock has two parameters: • • the time γ where clock edge 0 occurs, the cycle time τ between consecutive clock edges. For c ∈ N ∪ {−1} this defines the position e(c) of clock edge c as e(c) = γ + c · τ . Inspired by data sheets from hardware manufacturers, registers and gates have six timing parameters: • • • • • • 5 ρ: the minimal propagation delay of register outputs after clock edges, σ: the maximal propagation delay of register outputs after clock edges (we require 0 ≤ ρ < σ), ts: setup time of register input and clock enable before clock edges, th: hold time of register input and clock enable after clock edges, α: minimal propagation delay of gates, and β: maximal propagation delay of gates5 (we require 0 < α < β).

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