Download Computing Platforms for Software-Defined Radio by Waqar Hussain, Jari Nurmi, Jouni Isoaho, Fabio Garzia PDF

By Waqar Hussain, Jari Nurmi, Jouni Isoaho, Fabio Garzia

This e-book addresses Software-Defined Radio (SDR) baseband processing from the pc structure standpoint, supplying an in depth exploration of alternative computing structures by way of classifying varied methods, highlighting the typical good points regarding SDR requisites and via exhibiting execs and cons of the proposed options. It covers architectures exploiting parallelism via extending single-processor atmosphere (such as VLIW, SIMD, TTA approaches), multi-core structures allotting the computation to both a homogeneous array or a collection of specialised heterogeneous processors, and architectures exploiting fine-grained, coarse-grained, or hybrid reconfigurability.

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The NoC routers are asynchronous to reduce dynamic power consumption. Five general purpose VLIW cores perform channel estimation and MIMO3 decoding. Four 2 3 NoC: Network-on-Chip. MIMO: Multiple Input, Multiple Output. 32 G. Sievers et al. NoC nodes integrate 1 Mbit memory each and a DMA4 engine for data transfers. An ARM1176 CPU with floating-point support is used for control and scheduling. In addition, the MPSoC features four Fast Fourier Transform (FFT), three channel decoding, and two bit-level hardware accelerators.

This macro is completely pre-placed and pre-routed based on the synthesis results presented in this section. 57 mW. Up to now, two chip prototypes of the CoreVA CPU have been realized based on a 65 nm low-power technology. Data and instruction caches have a size of 16 kB each. The CoreVA-VLIW is based on a conventional standard-cell library and contains 3 The CoreVA-MPSoC: A Multiprocessor Platform for Software-Defined Radio 45 Fig. 8 Area requirements of CoreVA CPU configurations with varying number of MAC- and LD/ST-units (S, M, L = number of slots, MAC, LD/ST) Fig.

4). Each CPU can access the local data memories of all other CPUs in an NUMA9 fashion using the cluster interconnect [32]. Therefore, each CPU has a master interface to access the other CPUs, the network interface (NI, cf. Sect. 3), and an optional common shared memory [33]. In addition, each CPU has a slave interface for initialization and the external access of its local memories. The master and slaves of a cluster are connected via an interconnect fabric. The highest possible performance and lowest latency can be achieved if a full crossbar is used [28].

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